1. Technical Field of the Present Invention
The present invention generally relates to the design of integrated circuits, and more specifically, to the optimization of the layout of the integrated circuit.
2. Description of Related Art
The design and manufacture of integrated circuits has a multitude of steps each of which is dependent upon the successful completion of the prior step. One such step is the layout of the integrated circuit. The layout is subject to complex rules (base ground rules) that govern such things as the geometry of shapes on various process layers. The base ground rules can include minimum and/or maximum values for width, spacing, overlap requirements, and the like.
In general, a design that complies with the base ground rules can be manufactured in a particular technology with a certain degree of certainty. The exception arises with the introduction of new process technologies (especially those that are in the sub-wavelength regimes) where the minimums/maximums specified for the base ground rules may not be as accurate, especially, in the beginning of the technology cycle. In order to deal with the inaccuracies, manufacturing facilities provide recommended ground rules that are usually larger than the minimum or smaller than the maximum.
As a given manufacturing technology matures, manufacturing engineers assign priorities to the recommended ground rules according to the effect compliance has on manufacturing yield. Prioritization of these rules is critical to a designer since it is nearly impossible to comply with all the recommended ground rules and still have an intended design function appropriately. Any modification of a layout to comply with the recommended ground rules should be done according to the assigned levels of priority. Obviously, compliance with any base ground rule minimum/maximums take priority over recommended ground rules.
Current layout optimization programs optimize a layout by setting the target value for the optimization equal to the recommended ground rule. This creates several problems. First, this type of optimization fails to take into account the prioritization of the rules and their corresponding trade-offs. Second, it fails to allow a recommended ground rule to be partially satisfied. For example, if M1 minimum spacing is 0.20 microns and the recommended value is 0.25 microns then any spacing greater than 0.20 microns is an improvement. Unfortunately, the current optimization programs would use the 0.25 microns as the target and cause the optimizer to attempt to move all M1 spacings to 0.25 microns at the expense of distributing available space according to those recommended ground rules that would benefit the yield the most.
It would, therefore, be a distinct advantage to have a method, apparatus, and computer program product that would weight the minimum base ground rules and recommended ground rules according to their benefits and applies the optimization of the integrated circuit design according to this prioritization.